1. Field of the Invention
The present invention relates in general to electrostatic discharge (ESD) protection for integrated circuits, and especially to silicon controlled rectifier (SCR) structures fabricated in SOI technology for providing electrostatic discharge protection to integrated circuits.
2. Description of the Prior Art
Recent advances in integrated circuits have included the further development of silicon-on-insulator (SOI) technology, in which an insulator layer is embedded within a substrate and extends beneath the active regions of an integrated circuit. There are many advantages in SOI devices, including nearly perfect sub-threshold swing, latch-up free operation, low off-state leakage, low operating voltage, and high current driving ability. But, electrostatic discharge (ESD) presents an issue due to bad thermal conductivity of the buried oxide and its floating body effect.
ESD often causes damage to semiconductor devices on an integrated circuit during handling of the IC package. An electrostatic discharge often has an extremely high voltage that easily destroys the thin gate oxide of devices in CMOS IC""s. To prevent such ESD damage, the on-chip ESD protection circuits are typically incorporated into the chip of the integrated circuit. In general, such protection circuits include a switch that can be turned on and that is capable of conducting relatively large currents during an ESD event, but which stays turned off when the IC is under normal operating conditions. SCR devices typically have low holding voltages (Vholdxcx9c1V) in bulk (non-epitaxial) CMOS processes.
The power dissipation (power≈Iesd*Vhold) of the SCR device during ESD-related stress is thus less than that for other ESD protection devices (such as diodes, MOS""s, BJT""s or field-oxide devices) in CMOS technology. Therefore, SCR devices can sustain a much higher ESD level within a smaller layout area in CMOS IC""s, and have been used as the main ESD clamping devices in ESD protection circuitry.
Since SCR devices have a switching voltage that exceeds 30 volts in sub-micron CMOS processes, they are not suitable for protecting the gate oxides in sub-micron CMOS technology, which typically have a breakdown voltage of less than 20 volts. Additional secondary protection circuits are often added into an on-chip ESD protection circuit that uses a SCR device to provide the overall ESD protection functionality for the IC. In order to improve the protection efficiency of SCR devices, several modified designs have been disclosed that use SCR devices in on-chip ESD protection circuitry.
In U.S. Pat. No. 5,012,317, a SCR device realized in a P-substrate/N-well CMOS process is proposed. Please refer to FIG. 1. FIG. 1 is a cross-sectional schematic diagram of a SCR device 10 realized in a P-substrate/N-well CMOS process according to the prior art. As shown in FIG. 1, the SCR device 10 is made in a silicon substrate. The silicon substrate comprises a P-type substrate 11 and an N well 12 in the P-type substrate 11, a P+ region 14 in the N well 12 for use as an anode of the SCR device 10 (the input terminal of the SCR device 10), and an N+ region 15 in the P-type substrate 11 for use as a cathode of the SCR device 10 (the ground terminal of the SCR device 10). The P+ region 14, the N well 12, the P-type substrate 11 and the N+ region 15 form the SCR device 10. Such a SCR device is triggered on by the junction breakdown across the P-type substrate/N well junction. When the SCR device 10 is triggered on, ESD current flows from the P+ region 14, through the N well 12, through the P-type substrate 11, through the N+ region 15, and then to ground for discharging. As described above, such a SCR device often has a high switching voltage (greater than 30V in a 0.35 xcexcm CMOS process). With a higher switching voltage, the SCR device 10 needs an additional secondary protection circuit to provide the overall ESD protection functionality to the IC.
In U.S. Pat. No. 5,225,702, a modified design for a SCR device is proposed. Please refer to FIG. 2. FIG. 2 is a cross-sectional schematic diagram of a modified design of a SCR device 20 according to the prior art. As shown in FIG. 2, the modified SCR device 20 is made on a silicon substrate. The silicon substrate comprises a P-type substrate 21 with an N well 22 in the P-type substrate 21, a P+ region 24 in the N well 22 for electrically connecting to the anode, which is normally the input terminal, an N+ region 25 in the P-type substrate 21 for electrically connecting to the cathode, which is normally the ground terminal, and an N+ diffusion region 26 that is added across the P-type substrate/N well junction. The P+ region 24, the N well 22, the P-type substrate 21, the N+ region 25, and the additional N+ diffusion region 26 together form the modified SCR device 20. With the inserted N+ diffusion region 26, the switching voltage of this SCR 20 is reduced to the breakdown voltage across the N+ diffusion region/P-type substrate junction. Such a modified SCR device 20 typically has a switching voltage of about 12V for a 0.35 xcexcm CMOS process. With a lower switching voltage, the SCR device 20 can be triggered on more quickly to discharge ESD current.
In U.S. Pat. No. 5,453,384, another modification of a SCR device is proposed, with an NMOS device added across the P-type substrate/N well junction. Please refer to FIG. 3. FIG. 3 is a cross-sectional schematic diagram of a second modified design of a SCR device 30 according to the prior art. As shown in FIG. 3, the SCR device 30 is made on a silicon substrate. The silicon substrate comprises a P-type substrate 31 with an N well 32 in the P-type substrate 31, a P+ region 34 in the N well 32 for electrically connecting to the anode, which is normally the input terminal, an N+ region 35 in the P-type substrate 31 for electrically connecting to the cathode, which is normally the ground terminal, and an N+ diffusion region 36 across the N well 32 and the P-type substrate 31. The P+ region 34, the N well 32, the P-type substrate 31, and the N+ region 35 form the second modified design of the SCR device 30.
Compared to the previously described design for the SCR device 20, the SCR device 30 further comprises a gate insulator 37 together with a gate 38, which are formed between the N+ diffusion region 36 and the N+ region 35. Both a spacer 39 and a lightly doped drain 40 (in the P-type substrate 31) are formed on either side of the gate 38. An additional NMOS device 42 is thereby formed. In FIG. 3, shallow-trench-isolation (STI) regions 44 are also indicated in the structure of the SCR device 30 to indicate that such a SCR device 30 is formed using deep-submicron CMOS processes. With the additional NMOS device 42, the switching voltage of the SCR device 30 is reduced to the drain breakdown voltage of the inserted NMOS device 42 across the P-type substrate/N well junction. The SCR device 30 typically has a switching voltage of about 8V in 0.35 xcexcm CMOS processes. With a sufficiently lowered switching voltage, the SCR device 30 can protect an IC in a standalone configuration without the need for extra secondary protection circuits.
Continuous advances in silicon-on-insulator (SOI) techniques are being made, which brings eminent progress to IC process. The SOI technique involves the formation of an insulator layer (a buried oxide layer) in the substrate, which extends beneath the active doping region of the integrated circuit. SOI devices have many advantages, such as nearly perfect sub-threshold swing, latch-up free operation, a low off-state leakage, a low operating voltage, and high current driving capabilities. However, due to the poor thermal conductivity of the buried oxide layer, and its floating body effect, IC products manufactured with the SOI technique have more severe problems as regards reliability.
When utilizing the SOI technique, the p-n-p-n path of a SCR device is blocked by the buried oxide region or the STI region of the SOI CMOS process. Consequently, in U.S. Pat. No. 6,015,992, a bi-stable SCR-like device has been proposed. Please refer to FIG. 4.
FIG. 4 is a cross-sectional schematic diagram of a bi-stable SCR-like device 50 according to the prior art. As shown in FIG. 4, the SOI substrate comprises a substrate 60, a buried oxide layer 46 and a single crystal silicon layer 66. Two additional connection lines (line 52 and line 54) are present in the bi-stable SCR-like 50, which are used to connect the separated npn 56 and pnp 58 BJT to form a SCR-like device. The active doping regions 57, 59 are separated by a field oxide layer 63. One difference between a conventional SCR and the SCR-like bi-stable switch 50 is that the npn 56 and pnp 58 BJT must be formed in separate and isolated active regions, and therefore require an interconnect layer to form the entire SCR-like device. For this reason, this is not a true SCR device.
It is thus important to develop a novel SCR structures so as to realize a SCR device in SOI CMOS processes.
It is therefore a primary objective of the present invention to provide an NMOS-trigger silicon controlled rectifier for silicon-on-insulator (SOI-NSCR), and a PMOS-trigger silicon controlled rectifier for silicon-on-insulator (SOI-PSCR). Further, electrostatic discharge protection circuits utilizing the SOI-NSCR and SOI-PSCR are described.
It is yet another objective of the present invention to realize a silicon controlled rectifier in silicon-on-insulator that has a compact structure and a quick turn-on speed.
In the first preferred embodiment of the present invention, a SOI-NSCR comprises a P-type well and an N-type well in a single crystal silicon layer on the surface of a silicon-on-insulator substrate. A first P+ region and a first N+ region are in the N-type well for electrically connecting to the anode. A second P+ region and a second N+ region are in the P-type well for electrically connecting to the cathode. The first P+ region, the N-type well, the P-type well and the second N+ region form a lateral SCR. A third N+ region is across the N-type well and the P-type well and a gate is in the P-type well. The third N+ region, the gate and the second N+ region form an NMOS. A dummy gate is in the N-type well for isolating the first P+ region and the third N+ region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is generated from the N-type well to the P-type well, which results in the turning on of the SOI-NSCR. When applying a voltage to the third N+ region, a trigger current is formed, causing the lateral SCR to enter a latch state and trigger on the SOI-NSCR.
In a second preferred embodiment of the present invention, a PMOS replaces the NMOS in a relative manner so as to form a forward bias from the N-type well to the P-type, which results in the turning on of the SOI-PSCR. A third P+ region is used in the second preferred embodiment. When a voltage is applied to the third P+ region, a trigger current is formed so that the lateral SCR enters a latch state and triggers on the SOI-PSCR.